1. Field of the Invention
The present invention relates to a shifter, and particularly relates to a shifter that can avoid utilizing a partial pulse.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a prior art shifter 100. As shown in FIG. 1, the shifter 100 includes a plurality of shifting stages 101, 103, and 105 coupled in series. The shifting stage 101 samples a command signal CMD Φ according to an external clock signal CLKE (also named a free running clock signal). However, if all shifting stages utilize the external clock signal CLKE to sample the command signal, the external clock signal source must drive a large load, thus high power is needed.
Therefore, the shifter 100 may further includes a command triggering clock signal generating circuit 107 to generate a command triggering clock signal CLKC (also named a local clock signal). The command triggering clock signal CLKC is generated when a command signal arrives (such as CMD Φ in this embodiment). The command triggering clock signal CLKC does not run all the time but remains on during the time when the command signal shifts around the shifting stages. In the example of FIG. 2, the shifting stages after the shifting stage 101, that is, the shifting stages 103, 105, both utilize the triggering clock signal CLKC to sample the command signal output from the previous shifting stage.
However, the command triggering clock signal CLKC may have the issue of “partial pulse”. FIG. 2 is a schematic diagram illustrating the external clock signal CLKE and the command triggering clock signal CLKC applied to the shifter in FIG. 1. As shown in FIG. 2, the first pulse P1 of the command triggering clock signal CLKC may have an un-complete pulse width due to different paths for the external clock signal CLKE and the command signal CMDΦ. Such situation is called “partial pulse”. If such partial pulse is utilized to sample a command, the shifting stage may enter a unstable state, causing unexpected behavior at the output of this shifting stage. If this happens, it may corrupt the shift-chain and cause command-fail.
FIG. 3 is a timing diagram illustrating the relations between the clock signals and the command signals for the example shown in FIG. 1. The above-mentioned “partial pulse” issue can be understood more clearly via FIG. 3. AS shown in FIG. 3, the rising edge ed1 of the external clock signal CLKE is utilized to sample the command signal CMDΦ to generate a high level of the command signal CMD1. In a normal situation, the high level of the command signal CMD 2 is supposed to occur at the timing T1 via sampling the command signal CMD1 by the rising edge ed2 of the command triggering clock signal CLKC. However, in FIG. 3 the high level of the command signal CMD 2 occurs at a wrong timing T2 since the command signal CMD1 is sampled by the rising edge ed3 of the partial pulse P1. Accordingly, the command signal CMD2 is wrongly generated, therefore other command signals generated according to the command signal CMD2 may also have error.